A Low-Cost Stimulus Design for Linearity Test in SAR ADCs

被引：1

作者：

Chao, An-Sheng ^{[1
]}

Lin, Cheng-Wu ^{[1
]}

Ting, Hsin-Wen ^{[2
]}

Chang, Soon-Jyh ^{[1
]}

机构：

[1] Natl Cheng Kung Univ, Dept Elect Engn, Tainan 70101, Taiwan

[2] Natl Kaohsiung Univ Appl Sci, Dept Elect Engn, Kaohsiung 807, Taiwan

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2014年 / E97C卷 / 06期

关键词：

analog-to-digital converter (ADC); design for testability (DFT); pattern generator (PG); output response analyzer (ORA); TIME;

D O I：

10.1587/transele.E97.C.538

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The proposed stimulus design for linearity test is embedded in a differential successive approximation register analog-to-digital converter (SAR ADC), i.e. a design for testability (DFT). The proposed DFT is compatible to the pattern generator (P)) and output response analyzer (ORA) with the cost of 12.4-% area of the SAR ADC. The 10-bit SAR ADC prototype is verified in a 0.18-mu m CMOS technology and the measured differential nonlinearity (DNL) error is between -0.386 and 0.281 LSB at 1-MS/s.

引用

页码：538 / 545

页数：8

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