P-n junction periphery protection of 4H-SiC power p-i-n diodes using epitaxy and dry etching

In high voltage devices the breakdown voltage is reduced from its theoretical value by the occurrence of high electric field at the device p-n edge and therefore a further extension of the space charge is needed in this area. In the approach used in this work the p(+) epitaxial layer is extended over the main junction (5 mm(2) total area) and effects on its periphery by the total incorporated acceptor charge. We used saddle field fast atom beam (FAB) source for etching of the extended p(+) area, which allows precise control of the etched rate and respectively of the charge. Using a typical p(+)layer concentration of 8.10(18)cm(-3) the calculated thickness of extended p layer is 15 nm. At the same time, the measured reverse I-R-V-R characteristics at different stages of etching (different thickness of the extended p(+)layer) show that the optimal thickness is 150-200 mn. This non-coincidence is explained by the existence of an interface layer between n(o) and p(+) epitaxial layers, where the acceptor concentration is completely different from the average measured one. The diodes, prepared by the described method, have decreased reversed currents and increased breakdown voltage in comparison with the vertical mesa design diodes. Our experimental results show that the proposed method is effective and more applicable for protection of the junction edge of high voltage SiC diodes.