Effects of drain bias on threshold voltage fluctuation and its impact on circuit characteristics

被引：0

作者：

Miyamura, Makoto ^{[1
]}

Nagumo, Toshiharu ^{[2
]}

Takeuchi, Kiyoshi ^{[2
]}

Takeda, Koichi ^{[2
]}

Hane, Masarni ^{[2
]}

机构：

[1] NEC Corp Ltd, Device Platforms Res Labs, 1120 Shimokuzawa, Kanagawa 2291198, Japan

[2] NEC Elect Corp, LSI Fundamental Res Lab, Kanagawa, Japan

来源：

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2008, TECHNICAL DIGEST | 2008年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Enhancement mechanism of Vth fluctuation in saturation region is analyzed through addressable transistor array measurement and 3D Monte-Carlo TCAD simulation. It was confirmed that random dopant fluctuation (RDF) in heavily doped halo devices enhances source-drain asymmetry, resulting in non-Gaussian distributions of DIBL and saturation Vth (Vth_sat). The measured DIBL behavior was accurately modeled and implemented in statistical circuit simulation, to evaluate the impact on SRAM stability. Optimization of halo for mitigating RDF is important for achieving aggressively scaled SRAM cells.

引用

页码：447 / +

页数：3

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