Heuristic algorithm for reducing mapping sets of hardware-software partitioning in reconfigurable system

One of many technical challenges facing the designers of reconfigurable systems is how to integrate hardware and software resources. The problem of allocating each application function to general purpose processors (GPPs) and Field Programmable Gate Array (FPGAs) considering the system resource restriction and application requirements becomes harder. We propose a solution employing Y-chart design space exploration approach to this problem and develop Y-Sim, a simulation tool employing the solution. Its procedure is as follows: First, generate the mapping set by matching each function in a given application with GPPs and FPGAs in the target reconfigurable system. Secondly, estimate throughput of each mapping case in the mapping set by simulation. With the simulation results, the most efficient configuration achieving the highest throughput among the mapping cases would be chosen. We also propose HARMS (Heuristic Algorithm for Reducing Mapping Sets), a heuristic algorithm minimizing the mapping set by eliminating unnecessary mapping cases according to their workload and parallelism to reduce the simulation time overhead. We show the experimental results of proposed solution using Y-Sim and efficiency of HARMS. The experiment results indicates that HARMS can minimize the mapping set by 87.5% and most likely pick out the mapping case with the highest throughput.