Performance of Asynchronous Double-gate Poly-Si Thin-film Transistors

In our simulation, double-gate polycrystalline silicon thin-film transistors(DG p-Si TFTs) have been studied. We consider the effect of grain boundaries between the grains of polycrystalline silicon, and compared with the experiment. Then, considering the conventional work mode of the double-gate TFTs (DG TFTs), we compare the transfer characteristics of the DG TFT and traditional single-gate TFT (SG TFT). For the channel, the W/L equals to 1.5 mu m/1.5 mu m, the top and bottom SiO2 gate layer are same thickness 100nm. Also, the channel layer is intrinsic silicon and the thickness is 100nm. The DG TFT presents' a significant improvement in current drive and a steeper subthreshold slope. Mainly, we also demonstrate a novel asynchronous working mode, in which the back gate (V-BG) is settled to a fixed voltage. The back gate play a role of precharging the TFT, and we find a larger V-BG leads to a lower threshold voltage. Meanwhile, it should be observed that a large V-BG also results in a decrease of on/off ratio and a deterioration of the subthreshold slope. Thus, the compromise during the threshold voltage, on/off ratio and subthreshold slope is in need.