A Framework for Memory-aware Multimedia Application Mapping on Chip-Multiprocessors

The relentless increase in multimedia embedded system application requirements as well as improvements in IC design technology have motivated the deployment of chip multiprocessor (CMP) architectures. Task scheduling and data placement in memory are two of the most important steps in the application customization process as they greatly influence overall power consumption, and performance. Most designers consider task scheduling and data placement to be independent of each other. However, optimal task scheduling does not always produce optimal data placement, and optimal data placement may not necessarily allow for optimal task scheduling. In this paper, we propose a novel framework for simultaneous application mapping and data placement onto CMP architectures, especially for multimedia applications. At the core of our framework is a memory-aware task scheduling algorithm that relies on static analysis and task splitting to reduce off-chip memory transfers. Our experiments on a JPEG2000 case study have shown that we can achieve up to 35% performance Improvement and up to 66% power reduction compared to traditional scheduling/data allocation approaches.