A Monitoring-Aware Network-on-Chip Design Flow

被引：0

作者：

Ciordas, Calin ^{[1
]}

Hansson, Andreas ^{[1
]}

Goossens, Kees ^{[2
]}

Basten, Twan ^{[1
]}

机构：

[1] Eindhoven Univ Technol, NL-5600 MB Eindhoven, Netherlands

[2] Philips Res Labs Eindhoven, Eindhoven, Netherlands

来源：

DSD 2006: 9TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS, PROCEEDINGS | 2006年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Networks-on-chip (NoC) are a scalable interconnect solution for systems on chip and are rapidly becoming reality. Monitoring is a key enabler for debugging or performance analysis and quality-of-service techniques. The NoC design problem and the NoC monitoring problem cannot be treated in isolation. We propose a monitoring-aware NoC design flow able to take into account the monitoring requirements in general. We illustrate our flow with a debug driven monitoring case study of transaction monitoring. By treating the NoC design and monitoring problems in synergy, the area cost of monitoring can be limited to 3-20% in general.

引用

页码：97 / +

页数：2

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