A Low-Area Direct Memory Access Controller Architecture for a RISC-V Based Low-Power Microcontroller

In this work, we present a low area DMA controller that enables low-cost SoCs where subsystems need constant memory access. Small interfaces and a unique FIFO handling read/write transactions are fundamental blocks in this design. As proof of concept, the testing system also includes a RISC-V RV32IM processor, a USB 1.1/2.0 PHY and a QSPI interface. We implemented a whole microcontroller using a TSMC 0.18 mu m technology node, where the DMA occupies 4.2% of the total area. The results show a total DMA area of 1997 gates using 4 information channels, which is 75.3% smaller area in comparison with recent low-area DMAs.