A 3.3-V, 10-b, 25-MSample/s two-step ADC in 0.35-μm CMOS

被引：19
|
作者：
van der Ploeg, H [1 ]
Remmers, R [1 ]
机构：
[1] Philips Res Labs, NL-5656 AA Eindhoven, Netherlands
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1999年 / 34卷 / 12期
关键词：
analog-to-digital (A/D) converters; CMOS integrated circuits; data converters; flash A/D converters;
D O I：
10.1109/4.808905
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper describes the design of a two-step analog-to-digital converter (ADC), By using techniques such as improved switching and offset-compensated amplifiers, the high-speed two-step architecture can be expanded toward high resolution. The ADC presented here achieves 9 ENOB with a spurious-free dynamic range of more than 72 dB, ata sample rate of 25 MSample/s, The ADC is realized in a 0.35-mu m mainstream CMOS process without options such as double poly,It measures 0.66 mm(2) and dissipates 195 mW from a 3.3-V power supply.
引用
收藏
页码：1803 / 1811
页数：9
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