Hardware Design and Implementation of DOA Estimation Algorithms for Spherical Array Antennas

In order to meet the demands for direction of arrival (DOA) estimation in high-altitude platforms (HAPs) communication systems, a DOA estimator using field programmable gate array and digital signal processor (FPGA + DSP) hardware architecture for a 16-element spherical array on aerial platform is presented in this paper. The 16 channel received intermediate frequency (IF) signals are acquired by AD9233 at 35M samples/s, then the digital down conversion (DDC) module and IQ demodulation module are completed by using coordinate rotation digital computing (CORDIC) methods on the Altera EP3C120F780 Cyclone III FPGA, and a multiple signal classification (MUSIC) DOA estimation algorithm with sub-array divided techniques is implemented on the TI TMS320C6713 floating-point DSP. Hardware simulation shows that the proposed DOA estimator can achieve better performance in real-time computing and DOA estimation accuracy.