Design and Analysis of TSPC D flip-flop Based High Speed Frequency Divider Using 32 nm CMOS Technology

Frequency divider is digital circuit which is widely used in wireless communication, frequency dividers can be realized by using flip flops such as toggle type or delay type flip flops. We have tested the utilization of a true single phase clocking (TSPC) technique based D Flip-Flop implemented as a high-frequency divider-by-2 circuit. This divider consists of one TSPC D-flip-flops (D-FF). To achieve high-speed operations as well as downsize the circuit, the NOR functions are implemented into the TSPC D-FF. We have designed the frequency divider using 32nm CMOS process. The power consumption and operating frequency of the proposed divider was investigated. In the measurements, we have confirmed that the frequency is divided by 2 at higher frequency of 10 GHz clock with power consumption of 71.9065 nW. The circuit is implemented for the purpose of low-power high-frequency division applications for wireless local area netwok applications.