Phase noise in digital frequency dividers

This paper presents a physical derivation of phase noise in source-coupled-logic frequency dividers. This analysis takes into account both white and flicker noise sources and is verified on two 32/33 dual-modulus prescalers integrated in a 0.35-mum CMOS process. Design techniques for high-speed and low-noise operation are provided. The two integrated prescalers are identical apart from a synchronizing flip-flop at the output of one of them. The measured phase spectra are in good agreement with the estimates and demonstrate that the final synchronization allows a better trade-off between noise and power consumption. The maximum operating frequency is 3 GHz, the power consumption is 27 mW and the phase noise floor is - 163 dBc/Hz referred to the 78-MHz output.