Low power and write-enhancement RHBD 12T SRAM cell for aerospace applications

In aerospace applications, the conventional Static Random Access Memories (SRAMs) are facing high soft error problems like a single event upset. Several radiation-hardened based design (RHBD) like twelve-transistor (12T) Dice, 12T We-Quatro SRAM cells, etc., had been developed to address the soft error problems. But they all are consuming comparatively more total and static power with more delay and area. The 10T SRAM cell had been developed to reduce the power dissipation and area overhead. But the analysis of 10T cell shows a write failure at high-frequency. An RHBD 12T SRAM cell has been proposed in this paper. The proposed 12T SRAM cell consumes less total, and static power dissipation compared to 12T We-Quatro and 12T Dice cell, respectively. The critical charge and hold noise margin of the proposed SRAM cell have been improved compared to We-Quatro and Dice cell. The simulated result shows that the proposed SRAM cell has provided the less and comparable area, high write speed, and good writability under process variations. Finally, the Monte Carlo Simulation of SRAM cells under 45 nm CMOS technology validates the efficiency of the 12T proposed cell.