7.4μW Ultra-High Slew-rate Pseudo Single-Stage Amplifier Driving 0.1-to-15nF Capacitive Load with >69° Phase Margin

被引：0
|
作者：
Hong, Sung-Wan [1 ,2 ]
Cho, Gyu-Hyeong [2 ]
机构：
[1] Samsung Elect DMC R&D Ctr, Seoul, South Korea
[2] Korea Adv Inst Sci & Technol, Seoul, South Korea
来源：
2015 SYMPOSIUM ON VLSI CIRCUITS (VLSI CIRCUITS) | 2015年
关键词：
D O I：
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中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
To achieve ultra-high slew-rate with stable operation under wide capacitive load range, pseudo single-stage amplifier is proposed in this paper. The proposed amplifier achieves widest capacitive load drivability (x150). Also, this work achieves at least 151 times larger FOM for slew-rate compared to state-of-the-art works. This chip was fabricated using a 0.18 mu m CMOS process with area of 0.0021 mm(2).
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页数：2
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