A Low Power Multi-mode CMOS Image Sensor with Integrated On-chip Motion Detection

In this paper, we purpose a novel low power multi-mode CMOS smart image sensor node with integrated focal-plane motion detection and video compression. An 80x80 image pixel array is fabricated in 0.5 mu m 3M2P standard CMOS technology, occupying 3x3 mm(2) silicon area. The proposed imager enables various operational modes, including 1) event generator mode, 2) motion tracking mode and 3) video output mode in full-resolution or compression by region of interest (ROI). An ultra low power focal-plane motion detection block, consisting of analog memory and dual-threshold comparator, is integrated in the pixel-level circuit for on-chip motion detection. A hardware-friendly motion tracking algorithm is developed that indicates ROIs according to a strategy based on the detection results. A 12-bit on-chip, offarray ADC is employed to convert the captured light intensity into digital readouts. In order to further reduce the power consumption, lower image resolution is used under the first two modes. A trade-off analysis between the image resolution and detection accuracy is proposed in this paper. In simulation, the total power consumption is 10 mu W at a frame rate of 30fps and a supply voltage of 3.3V in motion tracking mode. A compression ratio of 14% and an average PSNR of 42dB is achieved in compressive video output mode.