Improved Bounds for Reduction to Depth 4 and Depth 3

Koiran [7] showed that if an n-variate polynomial of degree d (with d = n(O(1))) is computed by a circuit of size s, then it is also computed by a homogeneous circuit of depth four and of size 2(O(root d log(d) log(s))). Using this result, Gupta, Kamath, Kayal and Saptharishi [6] gave an exp (O(root d log(d) log(n) log(s))) upper bound for the size of the smallest depth three circuit computing an n-variate polynomial of degree d = n(O(1)) given by a circuit of size s. We improve here Koiran's bound. Indeed, we show that if we reduce an arithmetic circuit to depth four, then the size becomes exp (O(root d log(ds) log(n) )). Mimicking the proof in [6], it also implies the same upper bound for depth three circuits. This new bound is not far from optimal in the sense that Gupta, Kamath, Kayal and Saptharishi [5] also showed a 2(Omega)(root d) lower bound for the size of homogeneous depth four circuits such that gates at the bottom have fan-in at most root d. Finally, we show that this last lower bound also holds if the fan-in is at least root d.