Model checking of Signal Interpreted Petri Nets

被引:0
|
作者
Weng, XY [1 ]
Litz, L [1 ]
机构
[1] Univ Kaiserslautern, Inst Proc Automat, Kaiserslautern, Germany
关键词
logic control; model checking; temporal logic; Petri net;
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
In this paper we present an approach to verify the properties of a specification for logic control design with Signal Interpreted Petri Net (SIPN) applying temporal logic model checking methods, which also allows to study the unstable cycle in the design.
引用
收藏
页码:2748 / 2752
页数:5
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