Modeling of Threshold Voltage for 3D Double Gate Fully Depleted SOI MOSFET

被引：0

作者：

Goel, Neha ^{[1
]}

Pandey, Manoj Kumar ^{[2
]}

机构：

[1] SRM IST, Elect & Commun, NCR Campus, Ghaziabad, India

[2] Amity Sch Sci & Technol, Noida, India

来源：

2019 6TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND INTEGRATED NETWORKS (SPIN) | 2019年

关键词：

Fully Depleted SOI; 3D analytical model; SCE; Bulk CMOS; Threshold voltage (V-t); Back Gate Oxide thickness; Front Gate oxide thickness; Drain to source voltage; BODY;

D O I：

10.1109/spin.2019.8711771

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

With regular scale down of semiconductor devices continuously, when it reached in nanonzeter regime, threshold voltage changes because of SC'E Back gate voltage plays a significant role for controlling of threshold voltage in such cases. In this paper three dimensional mathematical modeling of threshold voltage is presented, the 3D poisson's equation is solved by using separation of variable method, analytically with suitable boundary conditions Pr DG SOI MOSFET with the influence of biasing with back gate. In this work, changes in threshold voltage has been demonstrated with respect to channel length considering back and front gate oxide thickness, Drain to source voltages and how short channel effects can be suppressed with application of Back Gate bias voltage.

引用

页码：816 / 819

页数：4

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