Energy-performance tradeoffs for the shared memory in multi-processor systems-on-chip

Accesses to the shared memory in multi-processor systems-on-chip represent a significant performance bottleneck and source of energy consumption, because of the synchronization of the accesses as well as of their relative "distance" from the processors. While multi-port memories are usually employed to solve performance issues, no standard solution exists for energy issues. In this work, we propose an architecture for the shared memory that is based on application-speficic partitioning, which offers various energy-performance tradeoffs. The shared address space of the application is split into two, non-overlapping subsets which are mapped onto two distinct memory blocks. By properly tuning the point at which the address space is split, various solutions can be achieved with different levels of energy/performance tradeoffs. Experiments on a set of parallel benchmarks show that it is possible to achieve solutions with energy-delay product savings ranging from 40 to 62% (50% on average) with respect to a conventional, non-partitioned architecture.