A modified nanoelectronic spiking neuron model

Spiking neural networks (SNNs) first came to the attention of scientists due to the search for a structure capable of emulating more closely the behavior of the human brain. The biological nervous system has some characteristics that allow it to process a large amount of data very quickly. It is also a fault-tolerant system, with a high level of parallelism. Low power consumption is another feature of the human brain that is desirable for electronic circuits. In this context, several models of artificial spiking neurons were developed, aiming to construct networks able to combine the best characteristics of the human brain. Most of these models, however, lack validation in larger networks. This paper proposes the implementation of an SNN based on a nanoelectronic spiking neuron model developed in previous works. To validate the behavior of an isolated neuron in a network, logic gates (NOT, OR, AND, and XOR) are used as a benchmark. The goal of this paper is to present a feasibility study on the possibility of implementing such nanoelectronic spiking neuron networks based on this spiking neuron model. Nanoelectronics represents an appealing implementation due to the gains regarding occupied area and power consumption, which are inherent characteristics of this technology. The neuron model was modified for simulation at room temperature. An information code based on the amplitude of the pulses presented at the output of the neuron was developed. During deployment of this approach, some limitations regarding the neuron model were detected; some possible solutions are proposed as future work.