Silicon nanostructures patterned on SOI by AFM lithography

The actual trends in microelectronics are the reduction of the dimensions and the search of new devices standing upon new phenomena as in the case of a Single Electron Transistor (SET) that is based on the Coulomb blockade. The nowadays limitation for device dimensions is that we are reaching the resolution limits of the lithography techniques. To go beyond this problem, we use the Atomic Force Microscope (AFM) nanolithography. To all the advantages brought by this technique we add those of using a silicon-on-insulator (SOI) substrate. In this article we are showing an example of a nanostructure fabricated by this method. Transport measurements and simulations performed on the device are in good agreement. We demonstrate the potential of using AFM lithography fabricated devices for applications like multigate transistors.