Memory Based Multiplier For Digital FIR Filter

被引:0
|
作者
Akana, Sujana Rani [1 ]
Jyothi, S. [1 ]
机构
[1] Shri Vishnu Engn Coll Women, Elect & Commun Engn, Bhimavaram, India
关键词
DSP; FIR filter; lut bsed multiplier;
D O I
暂无
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
Memory based structures are well-suited for many digital signal processing (DSP) applications, which involve multiplication with a fixed set of coefficients. In this paper a look-up-table (LUT)-multiplier-based approach for an efficient memory-based implementation of finite impulse response (FIR) filter is realized where the memory elements store all the possible values of products of the filter coefficients. Memory-based structures are more regular compared with the multiplyaccumulate Structures and have many other advantages of less area and reduced-latency implementation since the memory-access-time is much shorter than the usual multiplication-time compared to the conventional multipliers. In this paper this lut multiplier is compared with conventional multiplier like array multiplier using Xilinx which shows this memory based multiplier is having less no. of gates and less combinational delay.
引用
收藏
页数:5
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