Main Memory in HPC: Do We Need More or Could We Live with Less?

被引:27
|
作者
Zivanovic, Darko [1 ,4 ]
Pavlovic, Milan [1 ,4 ,6 ]
Radulovic, Milan [1 ,4 ]
Shin, Hyunsung [2 ]
Son, Jongpil [2 ]
McKee, Sally A. [3 ,5 ]
Carpenter, Paul M. [4 ]
Radojkovic, Petar [4 ]
Ayguade, Eduard [1 ]
机构
[1] Univ Politecn Cataluna, BSC, Barcelona, Spain
[2] Samsung Elect Co Ltd, Memory Div, 1-1,Samsungjeonja Ro, Hwaseong Si 445701, Gyeonggi Do, South Korea
[3] Chalmers Univ Technol, Gothenburg, Sweden
[4] Barcelona Supercomp Ctr, Jordi Girona 1-8,K2M 102, Barcelona 08034, Spain
[5] Chalmers Univ Technol, EDIT D&IT, Rannvagen 6,4th Floor, S-41296 Gothenburg, Sweden
[6] ASML, Eindhoven, Netherlands
关键词
Memory capacity requirements; high-performance computing; production HPC applications; HPL; HPCG;
D O I
10.1145/3023362
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
An important aspect of High-Performance Computing (HPC) system design is the choice of main memory capacity. This choice becomes increasingly important now that 3D-stacked memories are entering the market. Compared with conventional Dual In-line Memory Modules (DIMMs), 3D memory chiplets provide better performance and energy efficiency but lower memory capacities. Therefore, the adoption of 3D-stacked memories in the HPC domain depends on whether we can find use cases that require much less memory than is available now. This study analyzes the memory capacity requirements of important HPC benchmarks and applications. We find that the High-Performance Conjugate Gradients (HPCG) benchmark could be an important success story for 3D-stacked memories in HPC, but High-Performance Linpack (HPL) is likely to be constrained by 3D memory capacity. The study also emphasizes that the analysis of memory footprints of production HPC applications is complex and that it requires an understanding of application scalability and target category, i. e., whether the users target capability or capacity computing. The results show that most of the HPC applications under study have per-core memory footprints in the range of hundreds of megabytes, but we also detect applications and use cases that require gigabytes per core. Overall, the study identifies the HPC applications and use cases with memory footprints that could be provided by 3D-stacked memory chiplets, making a first step toward adoption of this novel technology in the HPC domain.
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页数:26
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