Design of Efficient Mirror Adder in Quantum- Dot Cellular Automata

被引：0
|
作者：
Mishra, Prashant Kumar [1 ]
Chattopadhyay, Manju K. [1 ]
机构：
[1] Devi Ahilya Univ, Sch Elect, VLSI Design & Embedded Syst Lab, Indore, Madhya Pradesh, India
来源：
3RD INTERNATIONAL CONFERENCE ON COMMUNICATION SYSTEMS (ICCS-2017) | 2018年 / 331卷
关键词：
Nanotechnology; quantum-dot cellular automata (QCA); Mirror Adder; Full Adder;
D O I：
10.1088/1757-899X/331/1/012010
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Lower power consumption is an essential demand for portable multimedia system using digital signal processing algorithms and architectures. Quantum dot cellular automata (QCA) is a rising nano technology for the development of high performance ultra-dense low power digital circuits. QCA based several efficient binary and decimal arithmetic circuits are implemented, however important improvements are still possible. This paper demonstrate Mirror Adder circuit design in QCA. We present comparative study of mirror adder cells designed using conventional CMOS technique and mirror adder cells designed using quantum-dot cellular automata. QCA based mirror adders are better in terms of area by order of three.
引用
收藏
页数：8
相关论文
共 50 条
  • [1] Design of Efficient Full Adder in Quantum-Dot Cellular Automata
    Sen, Bibhash
    Rajoria, Ayush
    Sikdar, Biplab K.
    [J]. SCIENTIFIC WORLD JOURNAL, 2013,
  • [2] Efficient Design of a Hybrid Adder in Quantum-Dot Cellular Automata
    Pudi, Vikramkumar
    Sridharan, K.
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 19 (09) : 1535 - 1548
  • [3] An Efficient Quantum-Dot Cellular Automata Adder
    Bruschi, Francesco
    Perini, Francesco
    Rana, Vincenzo
    Sciuto, Donatella
    [J]. 2011 DESIGN, AUTOMATION & TEST IN EUROPE (DATE), 2011, : 1220 - 1223
  • [4] Design of novel efficient adder and subtractor for quantum-dot cellular automata
    Hayati, Mohsen
    Rezaei, Abbas
    [J]. INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 2015, 43 (10) : 1446 - 1454
  • [5] Efficient Design of a Coplanar Adder/Subtractor in Quantum-dot Cellular Automata
    Sangsefidi, Milad
    Karimpour, Morteza
    Sarayloo, Mandiyar
    [J]. UKSIM-AMSS NINTH IEEE EUROPEAN MODELLING SYMPOSIUM ON COMPUTER MODELLING AND SIMULATION (EMS 2015), 2015, : 456 - 461
  • [6] An Efficient Design of Adder/Subtractor Circuit using Quantum Dot Cellular Automata
    Bardhan, Rajon
    Sultana, Tania
    Lisa, Nusrat Jahan
    [J]. 2015 18TH INTERNATIONAL CONFERENCE ON COMPUTER AND INFORMATION TECHNOLOGY (ICCIT), 2015, : 495 - 500
  • [7] Area Efficient BCD adder in Quantum dot Cellular Automata
    Ramesh, B.
    Asharani, M.
    Srujana, V.
    Chaithanya, P.
    Rajaiah, U.
    [J]. PROCEEDINGS OF THE 2016 2ND INTERNATIONAL CONFERENCE ON CONTEMPORARY COMPUTING AND INFORMATICS (IC3I), 2016, : 178 - 181
  • [8] Cost-Efficient Decimal Adder Design in Quantum-dot Cellular Automata
    Liu, Weiqiang
    Lu, Liang
    O'Neill, Maire
    Swartzlander, Earl E., Jr.
    [J]. 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), 2012, : 1347 - 1350
  • [9] An efficient design of full adder in quantum-dot cellular automata (QCA) technology
    Mohammadi, Mohammad
    Mohammadi, Majid
    Gorgin, Saeid
    [J]. MICROELECTRONICS JOURNAL, 2016, 50 : 35 - 43
  • [10] Efficient Design of Decimal Full Adder Using Quantum-dot Cellular Automata
    Li, Zeqiang
    Chu, Zhufei
    Wang, Lunyao
    Xia, Yinshui
    [J]. 2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2018, : 1373 - 1375
12345