Learning hardware using multiple-valued logic - Part 1: Introduction and approach

被引：8
|
作者：
Perkowski, M [1 ]
Foote, D
Chen, QH
Al-Rabadi, A
Jozwiak, L
机构：
[1] Portland State Univ, Portland, OR 97207 USA
[2] Eindhoven Univ Technol, NL-5600 MB Eindhoven, Netherlands
来源：
IEEE MICRO | 2002年 / 22卷 / 03期
关键词：
D O I：
10.1109/MM.2002.1013303
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Building intelligent robots will ultimately require developing real-time hardware realizations of exact or high-quality approximate algorithms for NP combinatorial problems. A new approach that combines hardware realization of such algorithms with learning in reconfigurable hardware is introduced. The approch uses combinatorial synthesis methods developed within the framework of the logic synthesis in digital-circuit-design automation.
引用
收藏
页码：41 / 51
页数：11
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