Toward an Energy-Efficient High-Voltage Compliant Visual Intracortical Multichannel Stimulator

被引:8
|
作者
Hasanuzzaman, Md. [1 ]
Motlagh, Bahareh G. [1 ]
Mounaim, Faycal [1 ]
Hassan, Ahmad [1 ]
Raut, Rabin [2 ]
Sawan, Mohamad [1 ]
机构
[1] Polytech Montreal, Elect Engn Dept, Polystim Neurotech Lab, Montreal, PQ H3T 1J4, Canada
[2] Concordia Univ, Dept Elect & Comp Engn, Montreal, PQ H3G 1M8, Canada
关键词
Energy-efficient stimuli-generator (SG); high-impedance microelectrode driver; high-voltage compliance; implantable biomedical device; intracortical microstimulation; microelectrode array (MEA); visual prosthesis; ELECTRICAL-STIMULATION; MICROELECTRODE ARRAYS; SYSTEM; CORTEX; MICROSTIMULATION; PROSTHESIS; DESIGN; CHIP; INTERFACE; IMPEDANCE;
D O I
10.1109/TVLSI.2018.2794445
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We present, in this paper, a new multichip system aimed toward building an implantable visual intracortical stimulation device. The objective is to deliver energy-optimum pulse patterns to neural sites with needed compliance voltage across high electrode-tissue interface impedance of implantable microelectrodes. The first chip is an energy-efficient stimuli generator (SG), and the second one is a high-impedance microelectrode array driver (MED) output stage. The four-channel SG produces rectangular, half-sine, plateau-sine, and other types of current pulse with stimulation current ranging from 2.32 to 220 mu A per channel. The microelectrode array driver is able to deliver 20 V per anodic or cathodic phase across the microelectrode-tissue interface for +/- 13V power supplies. The MED supplies different current levels with the maximum value of 400 mu A per input and 100 mu A per output channel simultaneously to 8-16 stimulation sites through microelectrodes, connected either in bipolar or monopolar configuration. Both chips receive power via inductive link and data through capacitive coupling. The SG and MED chips have been fabricated in 0.13-mu m CMOS and 0.8-mu m 5-/20-V CMOS/double-diffused metal-oxide-semiconductor technologies. The measured dc power budgets consumed by low-and mid-voltage chips are 2.56 and 2.1 mW consecutively. The system, modular in architecture, is interfaced with a newly developed platinum-coated pyramidal microelectrode array. In vitro test results with 0.9% phosphate buffer saline show the microelectrode impedance of 70 k Omega at 1 kHz.
引用
收藏
页码:878 / 891
页数:14
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