ROBUST WAFER-LEVEL THIN-FILM ENCAPSULATION OF MICROSTRUCTURES USING LOW STRESS PECVD SILICON CARBIDE

This paper presents a new low-cost, CMOS-compatible and robust wafer-level encapsulation technique developed using a stress-optimised PECVD SiC as the capping and sealing material, imparting harsh environment capability. This technique has been applied for the fabrication and encapsulation of a wide variety of surface-and thin-SOI microstructures that included microcavities, RF switches and various accelerometers. Advantages of our technique are its versatility, smaller footprint, reduced chip thickness and process complexity, post-CMOS batch processing capability and added functionality due to the possibility of integrating additional electrodes for MEMS. Besides fabrication details, this work also discusses related design aspects for large-area MEMS and demonstrates the encapsulation results. Successfully encapsulation of device geometries as large as 955x827 mu m(2) has been achieved.