An Enhanced Decoder for Multiple-Bit Error Correcting BCH Codes

With the advancement of device technology and decreasing the gap of memory cells, radiation particles may upset more multiple adjacent memory cells, and conventionally used BCH code in SRAM needs an improvement to correct the multiple bit soft errors. This paper proposes a novel high-speed BCH decoder that corrects triple-adjacent double-adjacent and single-bit errors in parallel and serially corrects multiple-bit errors other than adjacent errors the syndrome computation depend on the number of errors. The decoder has been implemented with a 130nm CMOS technology, and experimental results show that the proposed decoder incurs almost the same power and area overhead as compared to the conventional TEC BCH code serial decoder which corrects any double-bit errors in serial. What is more, the delay overheads incurred by the proposed parallel decoder is 50% lower than the serial decoder.