Design Methodology of an On-Chip Inductor in 180 nm CMOS Technology

被引：0

作者：

Brezovec, Ivan ^{[1
]}

Mikulic, Josip ^{[1
]}

Schatzberger, Gregor ^{[1
]}

Baric, Adrijan ^{[2
]}

机构：

[1] Ams AG, Tobelbader Str 30, A-8141 Premstaetten, Austria

[2] Univ Zagreb, Fac Elect Engn & Comp, Unska 3, Zagreb, Croatia

来源：

2019 42ND INTERNATIONAL CONVENTION ON INFORMATION AND COMMUNICATION TECHNOLOGY, ELECTRONICS AND MICROELECTRONICS (MIPRO) | 2019年

关键词：

LC resonator; on-chip inductor; electromagnetic simulations; Q-factor;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents the design methodology for an on-chip inductor in 180 nm CMOS technology, intended for a fully integrated LC oscillator. The design method uses the model based on the physical interpretation of the inductor, and optimizes the design with respect to the Q-factor. Resulting from the optimization procedure, the inductor is designed for the on-chip LC resonator, having the nominal inductance value of L-S=2.62 nH and Q-factor of 5.42 at 1 GHz. Finally, the designed inductor is verified by the EM simulations, and the results are compared to the physical model used for the optimization.

引用

页码：65 / 69

页数：5

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