A new cost-effective morphological filter chip

This paper proposes a new VLSI architecture for morphological filters and presents its design and implementation. The proposed architecture can significantly reduce hardware costs compared with existing architectures by using a feedback loop path to reuse partial results and a decoder/encoder pair comparator to detect minimum/maximum values. In addition, the proposed architecture requires one common architecture for both dilation and erosion and fewer number of operations. Moreover, it can be easily extended for larger size morphological operations. We developed VHDL models, performed logic synthesis using the SYNOPSYS(TM) CAD tool. We used the 0.8 mu m SOG cell library and performed function and timing simulations. The proposed morphological filter chip has been fabricated. The total number of gates is only 2,667 and the dock frequency is 30 MHz that meets real-time image processing requirements of the standard of ITU-R BT.601 image format.