Comments on and corrections to 'unified VLSI architecture for photo core transform used in JPEG XR'

In the Letter 'Unified VLSI architecture for photo core transform used in JPEG XR', the authors proposed a hardware architecture to implement the three elementary 2 x 2 transform operations for the photo core transform used in JPEG XR. However, there are some errors in their implementation, dataflow and reported resources used. In this Letter, we point out those errors and suggest the corresponding corrections. We also provide constant additions which must be added to the results of the implementation to conform the standard.