Ultrafast characterization of in-plane-gate field-effect transistors: Parasitics in laterally gated transistors

被引:2
|
作者
Ogawa, K
Allam, J
Baynes, ND
Cleaver, JRA
Mishima, T
Ohbu, I
机构
[1] HITACHI EUROPE LTD, HITACHI CAMBRIDGE LAB, CAVENDISH LAB, CAMBRIDGE CB3 0HE, ENGLAND
[2] UNIV CAMBRIDGE, MICROELECTR RES CTR, CAMBRIDGE CB3 0HE, ENGLAND
[3] HITACHI LTD, CENT RES LAB, KOKUBUNJI, TOKYO 185, JAPAN
关键词
D O I
10.1007/BF00820156
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In-plane-gate field-effect transistors are probed by femtosecond electrooptic sampling. Ultrafast response of the transistors is dominated by a displacement current induced by parasitic gate-drain capacitance. Intrinsic and parasitic gate-drain capacitances of various transistor structures are obtained from displacement-current characteristics and are in quantitative agreement with the calculation of planar capacitances. Intrinsic gate-drain capacitances are in the order of 100 aF, while parasitic gate-drain capacitances are between 1.7 and 4.8fF, more than ten times that of intrinsic gate-drain capacitances. Reduction in parasitic capacitance by a factor of two is achieved by means of grounded shields and is confirmed by calculation. The grounded-shields screen parasitic electric fields and transform parasitic coupling into a part of the waveguide coupling. This reduction in parasitic capacitance is the first demonstration that the parasitic field effect is controlled artificially by nanometre-scale device technology.
引用
收藏
页码:907 / 917
页数:11
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