Hardware and firmware developments for the upgrade of the ATLAS Level-1 Central Trigger Processor

被引：3

作者：

Anders, G. ^{[1
,2
]}

Bertelsen, H. ^{[3
]}

Boisen, A. ^{[3
]}

Childers, T. ^{[1
,2
]}

Dam, M. ^{[3
]}

Ellis, N. ^{[1
]}

Farthouat, P. ^{[1
]}

Ruiz, C. Gabaldon ^{[1
]}

Ghibaudi, M. ^{[1
,5
]}

Gorini, B. ^{[1
]}

Haas, S. ^{[1
]}

Kaneda, M. ^{[1
]}

Ohm, C. ^{[1
]}

Silva Oliveira, M. ^{[1
,6
]}

Pauly, T. ^{[1
]}

Poettgen, R. ^{[1
,4
]}

Schmieden, K. ^{[1
]}

Spiwoks, R. ^{[1
]}

Xella, S. ^{[3
]}

机构：

[1] CERN, CH-1211 Geneva, Switzerland

[2] Heidelberg Univ, D-69117 Heidelberg, Germany

[3] Univ Copenhagen, Niels Bohr Inst, DK-2010 Copenhagen, Denmark

[4] Johannes Gutenberg Univ Mainz, D-51222 Mainz, Germany

[5] Scuola Studi Super & Perfezionamento St Anna, I-56010 Pisa, Italy

[6] Univ Fed Juiz de Fora, BR-36036 Bairro San Pedro, Brazil

来源：

JOURNAL OF INSTRUMENTATION | 2014年 / 9卷

关键词：

Trigger concepts and systems (hardware and software); Digital electronic circuits;

D O I：

10.1088/1748-0221/9/01/C01035

中图分类号：

TH7 [仪器、仪表];

学科分类号：

0804 ; 080401 ; 081102 ;

摘要：

The Central Trigger Processor (CTP) is the final stage of the ATLAS first level trigger system which reduces the collision rate of 40 MHz to a Level-1 event rate of 100 kHz. An upgrade of the CTP is currently underway to significantly increase the number of trigger inputs and trigger combinations, allowing additional flexibility for the trigger menu. We present the hardware and FPGA firmware of the newly designed core module (CTPCORE+) module of the CTP, as well as results from a system used for early firmware and software prototyping based on commercial FPGA evaluation boards. First test result from the CTPCORE+ module will also be shown.

引用

页数：11

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