A digital video encoder chip which generates phase alternate (PAL) or National Television Standards Committee (NTSC) analog video output signals is presented. The chip operates from 3 to 5.5 V; typical differential gain and phase performance at 5 V is 0.4% and 0.2 degrees, respectively, and SNR is 66 dB rms. The architecture, circuit, and die size minimization techniques used to achieve this performance in a 4 x 4 mm CMOS die are presented. The die is packaged in a 44-pin plastic quad flatpack package (7 x 7 mm). The digital logic has 47k gates and achieves an average power dissipation of 0.37 mu W/gate/MHz. The paper also covers the circuit and packaging techniques used to reduce power, - J-A, and junction temperature in this package in order to allow continuous operation in still-air ambient temperatures of 70 degrees C.