Reconfigurable memory architecture for scalable IP forwarding engines

被引：2
|
作者：
Akhbarizadeh, M [1 ]
Nourani, M [1 ]
机构：
[1] Univ Texas, Ctr Integrated Circuits & Syst, Richardson, TX 75083 USA
来源：
ELEVENTH INTERNATIONAL CONFERENCE ON COMPUTER COMMUNICATIONS AND NETWORKS, PROCEEDINGS | 2002年
关键词：
D O I：
10.1109/ICCCN.2002.1043102
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, a reconfigurable memory architecture and lookup technique for IP packet forwarding engines is presented. This is a flexible technique that significantly elevates the scalability of the next generation network processors and other packet processing equipments, especially in terms of increased routing table sizes, increased traffic and bandwidth, increased frequency of route updates, and migration to IPv6.
引用
收藏
页码：432 / 437
页数：6
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