Performance targeted minimization of incompletely specified finite state machines for implementation in FPGA devices

A new method of the minimization of incompletely specified finite state machines (ISFSMs) is proposed. In this method, such optimization criterion as the critical delay path is taken into account already at the stage of minimizing internal states. In addition, the proposed method allows one to minimize the number of transitions and input variables of the FSM. The method is based on sequential merging of two internal states including the optimization criteria. Experimental results performed for two encoding styles show, that the maximum clock frequency of minimized FSMs is higher by 9% comparing to traditional methods.