Electromigration Simulation at Circuit Levels

Electromigration has been a dominant failure mechanism for interconnects in ULSI. Extensive research works on the understanding of electromigration and methodologies to enhance interconnect EM lifetime are being proposed. While the ultimate goal of all these studies are to extend the interconnect lifetime in ULSI, all the studies so far are on the test structures, with the belief that their effectiveness will be similar when implemented in circuit level. However, recent studies revealed that this may not be the case, and more considerations are needed when the methodologies are implemented in circuit level. This work shows the need for circuit level electromigration modelling and the method to perform the modelling at circuit level. Examples are shown for digital, analog and RF circuits, and the way to speed up the modelling in complex circuit is also presented, making the method practical for implementation.