The reliability margin of interconnects for advanced memory technologies

被引：0
|
作者：
Beyer, G. [1 ]
Demuynck, S. [1 ]
Stucchi, M. [1 ]
Ciofi, I. [1 ]
Toekei, Zs. [1 ]
机构：
[1] IMEC, Cu Low K Program, B-3001 Louvain, Belgium
来源：
SOLID STATE TECHNOLOGY | 2009年 / 52卷 / 05期
关键词：
Roughness measurement - Integrated circuit interconnects;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The trends of decreasing dimensions and new materials motivated the investigation of how these may affect the dielectric reliability of the interconnect structures. We posit that for a given supply voltage, the electrical field increases not only by the shrinking half-pitch, but also by the line edge roughness (LER) and misalignment of vias.
引用
收藏
页码：14 / +
页数：13
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