Monitoring of aging in integrated circuits by identifying possible critical paths

被引:14
|
作者
Lorenz, Dominik [1 ]
Barke, Martin [1 ]
Schlichtmann, Ulf [1 ]
机构
[1] Tech Univ Munich, Inst Elect Design Automat, D-80290 Munich, Germany
关键词
NBTI; SELECTION; IMPACT;
D O I
10.1016/j.microrel.2014.01.013
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Aging of integrated circuits can no longer be neglected in advanced process technologies. Especially the strong dependence of the delay degradation of digital circuits on the workload is still an unsolved problem. If the workload is not known exactly, only a worst-case design can guarantee that the circuit works correctly during the entire specified lifetime. We propose a method that enables a better-than-worst-case design. To assure that this design still works correctly during the specified lifetime, the circuit is monitored periodically and countermeasures are taken if the circuit degrades too much. Our main contribution is an algorithm to identify all paths that might become critical during the specified lifetime. These are called possible critical paths (PCPs). This is the first approach that also considers local process variations for finding the PCPs. Without considering process variations, it is not guaranteed that all possible critical paths are found. In addition, we could reduce the number of paths that have to be monitored by 2.7x compared to a state-of-the-art approach. (C) 2014 Elsevier Ltd. All rights reserved.
引用
收藏
页码:1075 / 1082
页数:8
相关论文
共 50 条
  • [1] Paths to Terahertz CMOS Integrated Circuits
    Shim, D.
    Mao, C.
    Han, R.
    Sankaran, S.
    Seok, E.
    Cao, C.
    Knap, W.
    Kenneth, O.
    PROCEEDINGS OF THE IEEE 2009 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2009, : 657 - +
  • [2] Early Selection of Critical Paths for Reliable NBTI Aging-Delay Monitoring
    Gomez, Andres F.
    Champac, Victor
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 24 (07) : 2438 - 2448
  • [3] Embedded Silicon Odometers for Monitoring the Aging of High-Temperature Integrated Circuits
    Majerus, Steve
    Tang, Xinyao
    Liang, Jifu
    Mandal, Soumyajit
    2017 IEEE NATIONAL AEROSPACE AND ELECTRONICS CONFERENCE (NAECON), 2017, : 98 - 103
  • [4] LATCHUP PATHS IN BIPOLAR INTEGRATED CIRCUITS.
    Baze, M.P.
    Johnston, A.H.
    IEEE Transactions on Nuclear Science, 1986, NS-33 (06)
  • [5] LATCHUP PATHS IN BIPOLAR INTEGRATED-CIRCUITS
    BAZE, MP
    JOHNSTON, AH
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1986, 33 (06) : 1499 - 1504
  • [6] Recent Advances in In-situ and In-field Aging Monitoring and Compensation for Integrated Circuits
    Seok, Mingoo
    Kinget, Peter R.
    Yang, Teng
    Li, Jiangyi
    Kim, Doyun
    2018 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2018,
  • [7] Identifying aging-aware representative paths in processors
    Sandionigi, Chiara
    Heron, Olivier
    2015 IEEE 21ST INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS), 2015, : 32 - 33
  • [8] Controlling Aging in Timing-Critical Paths
    Arasu, Senthil
    Nourani, Mehrdad
    Carulli, John M., Jr.
    Reddy, Vijay K.
    IEEE DESIGN & TEST, 2016, 33 (04) : 82 - 91
  • [9] CRITICAL PATHS IN CIRCUITS WITH LEVEL-SENSITIVE LATCHES
    BURKS, TM
    SAKALLAH, KA
    MUDGE, TN
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1995, 3 (02) : 273 - 291
  • [10] Fast identification of true critical paths in sequential circuits
    Ubar, Raimund
    Kostin, Sergei
    Jenihhin, Maksim
    Raik, Jaan
    Juerimaegi, Lembit
    MICROELECTRONICS RELIABILITY, 2018, 81 : 252 - 261