Systematic Methodology for the Design of Seevinck's CMOS Log-domain Integrators

This work presents a methodology for the design of Seevinck's CMOS log-domain integrators. Since companding circuits in general and log-domain circuits in particular impose many restrictions concerning the correct operating point of transistors and the perfect cancellation of nonlinearities, their dimensioning is not simple. In order not to such a difficulty become a drawback against the achievable low power consumption and high signal-to-noise(distortion) ratio, if compared to conventional small-signal circuits, a careful design methodology is required.