Multi-layer floorplanning for reliable system-on-package

Physical design automation for the new emerging mixed-signal System-on-Package (SOP) technology requires a new kind of floorplanner-it must place both active components such as digital IC, analog ICs, memory modules, MEMS, and opto-electronic modules, and embedded passive components such as capacitors, resistors, and inductors in a multi-layer packaging substrate while considering various signal integrity issues. We propose a new interconnect-centric multi-layer floorplanner named MF-SOP, which is based on a multiple objective stochastic Simulated Annealing method. The contribution of this work is first to formulate this new kind of floorplanning problem and then to develop an effective algorithm that handles various design constraints unique to SOP. The related experiments show that the area reduction of W-SOP compared to its 2-D counterpart is on the order of O(k) and wirelength reduction is 39% average for k-layer SOP, while satisfying design constraints.