Configurable symbol synchronizers for software-defined radio applications

In many synchronous receivers, symbol timing synchronization is achieved through implementation of art analog phase locked loop (PLL). A phase detector and voltage-controlled oscillator drive a reference signal to be in phase with the received training sequence. Due to the quick phase convergence this option is attractive: however, limitations in pre-packaged hardware make this approach infeasible at times. Changes in the received symbol rate in software radio applications can further complicate the hardware implementation by requiring additional control signals to alter the frequency of the reference signal. This paper examines a configurable symbol synchronizer for software-defined radio (SDR) architecture with a predefined RF front end. In this scenario, we implement a typical method for digital phase locking and make it adaptable to different data rates. A pre-synchronization step is used to provide a reasonable initial estimate for the received symbol period for lower, over-sampled data rates. This decreases the synchronization time while maintaining a constant sampling period at the ADC. It also maintains the down-conversion stage at the receiver. The paper shows the feasibility of this architecture to support wide range of symbol rates. (C) 2008 Published by Elsevier Ltd.