On-Line Monitoring of System Health Using On-Chip SRAMs as a Wearout Sensor

Safety critical systems need methodologies for chips to monitor their health in the field, so that the need for repairs can be determined during scheduled maintenance. Prior work provides health monitoring via detection of degradation. Since many wearout mechanisms provide no degradation signal, this paper proposes to use the embedded SRAM as a dynamic monitor of system health. The SRAM is monitored by detecting error correcting code (ECC) failures. The cause of ECC failures is diagnosed electrically with on-chip built-in self test (BIST). The time stamps and diagnosis data are combined to estimate process level wearout model parameters. The extracted wearout model parameters are combined with system wearout simulation data and the memory bit failures recovered by error correcting codes (ECC) to estimate the remaining lifetime of the entire processor. The estimation of the remaining life is helpful in monitoring potential chip failures in the near future, to ensure safe operation.