Energy-Aware Real-Time Tasks Processing for FPGA-Based Heterogeneous Cloud

被引:4
|
作者
Majumder, Atanu [1 ]
Saha, Sangeet [2 ]
Chakrabarti, Amlan [1 ]
McDonald-Maier, Klaus [2 ]
机构
[1] Univ Calcutta, Dept AK Choudhury Sch Informat Technol, Kolkata 700073, India
[2] Univ Essex, Sch Comp Sci & Elect Engn, Colchester CO4 3SQ, Essex, England
来源
基金
英国工程与自然科学研究理事会;
关键词
Cloud computing; Real-time systems; Servers; Field programmable gate arrays; Processor scheduling; Computer architecture; Task analysis; Field programmable gate arrays (FPGAs); service request; real-time scheduling; resource management; energy; heterogeneous cloud; CONSUMPTION;
D O I
10.1109/TSUSC.2021.3082189
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Cloud computing is becoming a popular model of computing. Due to the increasing complexity of the cloud service request, it often exploits heterogeneous architecture. Moreover, some service requests (SRs)/tasks exhibit real-time features, which are required to be handled within a specified duration. Along with the stipulated temporal management, the strategy should also be energy efficient, as energy consumption in cloud computing is challenging. In this paper, we have proposed a strategy, called "Efficient Resource Allocation of Service Request" (ERASER) for energy efficient allocation and scheduling of periodic real-time SRs on cloud platform. The cloud platform is consists of Field Programmable Gate Arrays (FPGAs) as Processing Elements (PEs) along with the General Purpose Processors (GPP). We have further proposed, an SR migration technique to reduce the tasks rejection by serving maximum SRs. Simulation based experimental results demonstrate that the proposed methodology is capable to achieve upto 90 percent resource utilization with only 26 percent SR rejection rate over different experimental scenarios. Comparison results with other state-of-the-art techniques reveal that the proposed strategy outperforms the existing technique with 17 percent reduction in SR rejection rate and 21 percent reduction in energy consumption. Further, the simulation outcomes have been validated on real FPGA test-bed based on Xilinx Zynq SoC with standard benchmark tasks.
引用
收藏
页码:414 / 426
页数:13
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