Digital Interpolator Implementation in VHDL

In this article we describe a creation, modeling, implementation and simulation of a digital interpolator. It will be used as a part of advanced radio transmission system. The input part of the system receiving part provides correct complex envelope sampling that is necessary for consequent signal processing. During the re-sampling, an interpolator co-operates with symbol timing estimator. It estimates correct sampling timing and controls an interpolator. We describe the process of interpolator modeling in Matlab in both floating and fixed point arithmetics for later implementation in the VHDL language for FPGA. The complete system was simulated in ISim, compared with the model and results are presented.