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- [1] Variation Tolerant Logic Mapping for Crossbar Array Nano Architectures 2010 15TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2010), 2010, : 865 - 870
- [2] Runtime Analysis for Defect-tolerant Logic Mapping on Nanoscale Crossbar Architectures 2009 IEEE/ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES, 2009, : 75 - 78
- [3] Defect-tolerant Logic Mapping on Nanoscale Crossbar Architectures and Yield Analysis IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE VLSI SYSTEMS, PROCEEDINGS, 2009, : 322 - 330
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- [6] A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays IEEE TRANSACTIONS ON MULTI-SCALE COMPUTING SYSTEMS, 2018, 4 (04): : 522 - 532
- [7] Defect-tolerant Logic with Nanoscale Crossbar Circuits Journal of Electronic Testing, 2007, 23 : 117 - 129
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- [9] Fault-Tolerant Neuromorphic Computing on Nanoscale Crossbar Architectures 2022 IEEE INFORMATION THEORY WORKSHOP (ITW), 2022, : 202 - 207