Performance of an Intuitive Hash Table in Shared-Memory Parallel Programs

Much research has been done and effort expended to design associative arrays or "hash tables" for parallel architectures. These efforts focus on a variety of techniques, including data distribution patterns, data access patterns, tiny changes to the hash function and the buffering of accesses. These efforts are not without merit, but the additional work laid on the programmer or the specialized nature of some of the layouts leads to a very low rate of return. Considering the push for modern parallel programming languages which abstract away the underlying architecture, a more intuitive version of the hash table is appropriate. We discuss the design and implementation of a hash table that is deliberately disconnected from the hardware. Performance of this design is evaluated along with recommendations for future work and usage.