Digital implementation of diode-clamped three-phase three-level SVPWM inverter

被引：0
|
作者：
Lin, L [1 ]
Zou, YP [1 ]
Zhang, J [1 ]
Zou, XD [1 ]
机构：
[1] Huazhong Univ Sci & Technol, Coll Elect & Elect Engn, Wuhan 430074, Peoples R China
来源：
PEDS 2003 : FIFTH INTERNATIONAL CONFERENCE ON POWER ELECTRONICS AND DRIVE SYSTEMS, VOLS 1 AND 2, PROCEEDINGS | 2003年
关键词：
digital control; diode-clamped multilevel inverter; SVPWM; switching loss;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The conventional modulation strategies for diode-clamped three-phase three-level inverter have some disadvantages, such as switching loss of switching device. This paper presents a novel space vector pulse width modulation (SVPWM) scheme to reduce switching loss. Using this novel modulation strategy, the changing of switch states cause only one single phase voltage change every time. In this way, the inverter generates similar output voltage as that under the common strategies, whereas the switching loss is reduced. The proposed scheme has been digitally implemented by using TMS320F240 and its feasibility has been verified by the experimental results.
引用
收藏
页码：1413 / 1417
页数：5
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