Technologies for Realisation of Ultra-thin Chips

被引：0
|
作者：
Kumaresan, Yogeenth [1 ]
Yogeswaran, Nivasan [1 ]
Dahiya, Ravinder [1 ]
机构：
[1] Univ Glasgow, Bendable Elect & Sensing Technol BEST Grp, Glasgow G12 8QQ, Lanark, Scotland
来源：
LATIN AMERICAN ELECTRON DEVICES CONFERENCE (LAEDC 2020) | 2020年
基金：
欧盟地平线“2020”; 英国工程与自然科学研究理事会;
关键词：
Protective layer; PDMS and ProTEK (c) B3; Ultrathin chip; Wet-etching; FLEXIBLE ELECTRONICS; E-SKIN; SILICON; CIRCUITS;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Ultra-thin chips (UTC) of silicon are a promising approach to address the immediate demand for the development of high performance flexible electronic systems. However, Si is brittle and rigid in nature, thereby limiting its application in flexible electronics. The mechanical flexibility could be induced to Si, by thinning it down to < 50 mu m. This paper presents an overview of post-processing steps adopted for realisation of UTC. In particular, we have focussed on wet-etching and two protective layers, namely ProTEK (c) B3 and polydimethylsiloxane (PDMS), which could be used as a low-cost method for protecting the front side of the wafer comprising of electronics devices.
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页数：4
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