Parallel total weight crossing number algorithm for channel routing on a linear array with a reconfigurable pipelined bus system

被引：1
|
作者：
Kimm, H
机构：
来源：
PROCEEDINGS OF THE TWENTY-NINTH SOUTHEASTERN SYMPOSIUM ON SYSTEM THEORY | 1997年
关键词：
D O I：
10.1109/SSST.1997.581604
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
In the channel routing problem, terminals between cells ave interconnected completely while reducing channel routing area. The crossing number, the number of crossings between two wires in the channel, is related to the channel routing area. In this paper; we present a parallel algorithm finding a weighted total crossing number in the channel by using LARPBS model (Linear Array with a Reconfigurable Pipelined Bus System), which is based on the advanced fiber optic technology. The parallel total weight crossing number algorithm on the LARPBS model runs in O(n*log(root n)) time using O(n) number of processors, where n is the number of nets in a channel.
引用
收藏
页码：183 / 187
页数：5
相关论文
共 44 条
  • [1] Parallel matrix multiplication on a linear array with a reconfigurable pipelined bus system
    Li, KQ
    Pan, VY
    IEEE TRANSACTIONS ON COMPUTERS, 2001, 50 (05) : 519 - 525
  • [2] Parallel matrix multiplication on a linear array with a reconfigurable pipelined bus system
    Li, Keqin
    Pan, Victor Y.
    Proceedings of the International Parallel Processing Symposium, IPPS, 1999, : 31 - 35
  • [3] Fast parallel selection on the linear array with reconfigurable pipelined bus system
    Han, YJ
    Pan, Y
    Shen, H
    FRONTIERS '99 - THE SEVENTH SYMPOSIUM ON THE FRONTIERS OF MASSIVELY PARALLEL COMPUTATION, PROCEEDINGS, 1999, : 286 - 293
  • [4] Parallel matrix multiplication on a linear array with a reconfigurable pipelined bus system
    Li, KQ
    Pan, VY
    IPPS/SPDP 1999: 13TH INTERNATIONAL PARALLEL PROCESSING SYMPOSIUM & 10TH SYMPOSIUM ON PARALLEL AND DISTRIBUTED PROCESSING, PROCEEDINGS, 1999, : 31 - 35
  • [5] An optimal and processor efficient parallel sorting algorithm on a linear array with a reconfigurable pipelined bus system
    He, Min
    Wu, Xiaolong
    Zheng, Si Qing
    COMPUTERS & ELECTRICAL ENGINEERING, 2009, 35 (06) : 951 - 965
  • [6] An optimal sorting algorithm on a linear array with reconfigurable pipelined bus system
    He, M
    Zheng, SQ
    PARALLEL AND DISTRIBUTED COMPUTING SYSTEMS, 2002, : 386 - 391
  • [7] Quicksort on a linear array with a reconfigurable pipelined bus system
    Pan, Y
    Hamdi, M
    SECOND INTERNATIONAL SYMPOSIUM ON PARALLEL ARCHITECTURES, ALGORITHMS, AND NETWORKS (I-SPAN '96), PROCEEDINGS, 1996, : 313 - 319
  • [8] Linear array with a reconfigurable pipelined bus system - Concepts and applications
    Pan, Y
    Li, KQ
    INFORMATION SCIENCES, 1998, 106 (3-4) : 237 - 258
  • [9] Mapping of ANNs on linear array with a reconfigurable pipelined bus system
    Cong, B
    INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED PROCESSING TECHNIQUES AND APPLICATIONS, VOLS I-III, PROCEEDINGS, 1997, : 522 - 529
  • [10] Repetitions detection on a linear array with reconfigurable pipelined bus system
    Seme, David
    Youlou, Sidney
    INTERNATIONAL JOURNAL OF PARALLEL EMERGENT AND DISTRIBUTED SYSTEMS, 2007, 22 (03) : 173 - 183
12345